Resume

Joseph David Tarango

EDUCATION

University of California, Riverside

Ph.D., M.S. Computer Science and Engineering

Adviser: Dr. Philip Brisk, Professor of Computer Science and Engineering.

Pertinent Knowledge: Apprentice Teaching, Algorithms and Data Structures, Advanced Computer Architecture, Advanced Computer Networks, Artificial Intelligence, Compiler Construction, Computer-Aided Electronic Circuit Simulation, Data Mining Techniques, Design and Architecture of Computer Systems, Design of Operating Systems, Digital Circuit Design, Discrete Structures, Electronic Circuits, Embedded and Real-Time Systems, Logic Design, Machine Learning, Machine Organization, Modeling and Simulation, NAND Memory, Network Routing, Phase Change Memory, Software and Hardware Engineering of Embedded Systems, Software Engineering, Solid State Electronics, Synthesis of Digital Systems, Reconfigurable Computing, Testing & Verification Techniques.

B.S. Computer Engineering

Adviser: Dr. Philip Brisk, Professor of Computer Science and Engineering.

Focus: Computer Architecture and Embedded Systems.

Project: Open RISC Processor Emulation Platform (FPGA)

Pertinent Knowledge: Assembly Programming, Algorithms, American Politics, Automata and Formal Languages, Biochemical Analysis, C++ Programming, Business Ethics, Formal Organizations, Concurrent Programming, Compiler Construction, Computer Architecture, Data Structures, Design of Integrated Circuits, Electrical Circuit Analysis, Embedded Systems, Logic Design, Machine Organization, Operating Systems, Modeling and Simulation of Dynamic Systems, Organic Chemistry, Real-Time Systems, Religious Myths and Rituals, Signals/Systems Analysis, Software and Hardware System Engineering, Solid State Electronics, Technical Communications, Technology in Pre-Modern civilizations, World History (Twentieth Century).

Crafton Hills College

A.S. Mathematics, Physics

Adviser: Dr. Matthew Adams, Professor of Physics and Astronomy

Focus: Applied Sciences

Pertinent Knowledge: Mechanics (Classical, Quantum Relativistic, Statistical), Electromagnetism, Thermodynamics, and Quantum Theory Calculus (Differential, Integral, Series, Vector, Multivariable, Specialized) Linear Algebra, Probability, Statistics Chemistry, English Composition and Critical Analysis, Hardware and Information Systems, A-plus (A+), Philosophy of Ethics and Moral Virtues, Sociology.

TECHNICAL & PROFESSIONAL EXPERTISE

Programming Languages: C, C++, Python, Verilog, and VHDL.

Compilers: ABC Synthesis, VPR (Verilog-to-Routing), Clang, TreeSitter, GCC/G++, LLVM/LLVM IR, Multi-Level Intermediate Representation (MLIR)

· Intel Corporation: (2013-Present), Machine Learning Engineer and Research Scientist

o Focus: Rapid Automation and Analysis for Developers (RAAD) through Machine Programming

o Expertise: Arithmetic, Artificial Intelligence, Compilers, Computer Architecture, Data Mining, Similarity Search, Machine Learning, Numerical Analysis, Persistent Memory (Optane), and System Architecture.

o Positions (Sorted oldest to newest)

§ Research Data Scientist in platform eco-systems using data mining, machine learning, artificial intelligence, and system architecture.

§ Technical Product Lead of core/system algorithms; University Program Project Director for Outreach, Recruiting, and Research

§ System Technical Product Lead for Path-finding, Fault Analysis, Research, and Development Engineer

§ Firmware Engineer (Intern)

o Technical Track Leadership:

§ Technical Lead for Persistent Memory domain in NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures (CAPA) NSF 16-606 https://www.nsf.gov/pubs/2016/nsf16606/nsf16606.htm

§ Domain Expert Researcher for SiFive through Intel Capital - Developed automated compilation flow and customs instruction application programming interface for data mining, artificial intelligence, machine learning, and similarity search. https://github.com/jtarango/freedom.git

§ Inventor of common telemetry architecture, reconfigurable architecture, and intelligence intervention systems.

§ Companywide Mentor Focused mentoring for prodigy technical engineers.

§ Principal Investigator for Rapid Automation and Analysis for Developers (RAAD)

Division Recognition Award(s) and Recognition(s) (Sorted oldest to newest):

§ Driving quality and reliability in Intel's first data center NVMe DC P3700 SSD.

§ Power management integrated circuit (PMIC) firmware for data center SSDs.

§ Robustness in garbage collection and wear-leveling in data center SSDs.

§ Strategy Acceleration Division Recognition Award For establishing 3D Component and Solid-State Drive (SSD) Models utilized by cross-platform teams within NSG and across Intel.

§ Driving the delivery of the first 3D NAND NVMe DC P3520 SSD.

§ Delivering a novel contribution in characterization and optimizations of the performance of data center SSDs.

§ Robustness in power loss and recovery algorithms in data center SSDs.

§ Co-delivering soft and hardware accelerated erase dwell time control systems.

§ Delivering state of the art architecture for safe shutdown in data center SSDs.

§ Delivering device time to ready auto tuning in data center SSDs.

§ Performance characterization of FPGA emulated SSD SoCs.

§ Development of the fastest and most comprehensive simulation, emulation, and power-on of a data center SSD SoC.

§ Co-development of a common architecture, rapidly prototyping, and delivering Telemetry in data center SSDs products.

§ Architecture of common data management methodology across all data center products.

§ Re-architecture and development of the content in the rapid analysis handbook.

§ Co-development of novel automation and tools.

§ Inventor and co-developer of cross-language compiler to auto decode machine data structure source and destination targets using LLVM.

§ Distinguished Inventor Patent Award for Deep Neural Network (DNN) technologies.

o University of Colorado, Boulder – (2019- Present) Industry Advisory Panel Member

o Collaborate with engineering departments to review content, propose changes, provide paths for collaboration within industry, industry context for novel research directions, and paths to communicate within technical leadership.

o Intel Capital – (2019-2020) Scientific Researcher and Engineering Advisor for SiFive (https://www.sifive.com/) and Intel Capital Embedded Engineering Program (EPP).

o Expert collaboration with SiFive Inc. under President of Engineering and Products Chris Lattner Ph.D. Developing automated FPGA compilation for customs instruction applications via programming interfaces for Data Mining, Artificial Intelligence, Machine Learning, and Similarity Search using Altera/Intel FPGAS. https://www.github.com/jtarango/freedom

o University of Colorado, Boulder – (2019) Adjunct Professor

o ECEN 5593 Advanced Computer Architecture

o https://sites.google.com/view/ecen5593-2019-fall/home

o UC Riverside – (2010-2018) Researcher

o Arithmetic optimization through compiler and hardware accelerators; the projects included prototyping algorithms to run on tightly coupled ASIC/FPGA and computing systems for similarity search algorithms.

o Teaching assistant for:CS161 & 161L Design and Architecture of Computing Systems, CS122A Intermediate Embedded and Real-Time Systems, EE/CS120B Introduction to Embedded Systems, CS61 Machine Organization and Assembly Language Programming, CS 8 Introduction to Computing, CS5 Introduction to Computer Programming

o National University of Singapore – (2012-2013) Researcher

o National Science Foundation (NSF) East Asia and Pacific Summer Institutes (EAPSI) collaborative research sponsored by Professor Tulika Mitra.

o University of Bern – (2010-2011) Internship

o Research internship to collaborate with Dr. Theo Kluter on the EPFL open RISC processor project.

o Jacquard Computing – (2008-2010) - Researcher:

o Research Assistant for Dr. Walid Najjar (UC Riverside Professor) on Riverside Optimizing Compiler for Configurable Computing (ROCCC). ROCCC is a C to VHDL compiler, which enables C programs to be translated to high-speed FPGA platforms. Systems including: Intel-Altera, Convey, Pico, Xilinx FPGAs to generate system arithmetic data paths.

PUBLICATIONS & PATENTS

[CODES+ISSS] Instruction Set Extensions for Dynamic Time Warping

J. Tarango, E. Keogh, and P. Brisk International Conference on Hardware/Software Codesign and System Synthesis Montreal, Canada, September 29 -October 4, 2013.

[ICCAD] A Just-in-Time Customizable Processor

L. Chen, J. Tarango, T. Mitra, and P. Brisk International Conference on Computer-Aided Design San Jose, CA, USA, November 18-21, 2013

[ASILOMAR-SSC] Accelerating the Dynamic Time Warping Distance Measure using Logarithmic Arithmetic

J. Tarango, E. Keogh, and P. Brisk
Pacific Grove, CA, November 2-5, 2014

USPO 11069425 - Multi-level memory repurposing technology to process a request to modify a configuration of a persistent storage media

USPO 20210191726 - Methods And Apparatus For Continuous Monitoring Of Telemetry In The Field

USPO 20210157512 - Flexible Configuration Of Storage Device With Translation Language Set

USPO 20210073632 - Methods, Systems, Articles Of Manufacture, And Apparatus To Generate Code Semantics

USPO 20200379687 - Storage Device with Client Reconfigurable Protocol

USPO 20200226080 - Solid State Drive with External Software Execution to Effect Internal Solid-state Drive Operations

USPO 20200225857 - Techniques to Predict or Determine Time-to-ready For A Storage Device

USPO 20200218649 - Performance Configurable Nonvolatile Memory Set

USPO 20190043604 - Multi-level Memory Repurposing

USPO 20190042139 - Moving Average Valid Content On SSD

USPO 10795593, 20190042129 - Technologies for Adjusting the Performance of Data Storage Devices Based on Telemetry Data

USPO 20190042128 - Technologies Dynamically Adjusting the Performance of a Data Storage Device

REFERENCES

Jim Baca – Solidigm Principal Engineer

Chris Lattner – ModularAI, CEO

Philip Brisk – Professor UC Riverside

Justin Gottschlich – MerlyAI CEO & Chief Scientist

Frank Hady – Intel Fellow

Pradeep Dubey – Intel Senior Fellow

Other available upon request

Last Updated: June 29, 2023