CV

Objective: Strategy, Director, and/or Research Scientist in Machine Learning/Artificial Intelligence within Intelligent Ecosystems in Software, Firmware, and Hardware using Adaptive Machine Programming.

Research Interests: Artificial intelligence, compilers, computer architecture, dynamic time warping, embedded systems, optimization of integrated systems, reconfigurable computing, cache management, context state, garbage collection, journaling, instruction set extensions, media policy, machine learning, performance, power loss imminent, power loss recovery, similarity search, technological strategy, etc.

EDUCATION

Ph.D. Computer Science and Engineering, UC Riverside

Adviser: Dr. Philip Brisk, Professor of Computer Science and Engineering

Focus: Computer Architecture, Embedded Systems, Machine Learning, Numerical Analysis

Publications: https://scholar.google.com/citations?user=8IGxzlIAAAAJ

M.S. Computer Science and Engineering, UC Riverside

Adviser: Dr. Philip Brisk, Professor of Computer Science and Engineering

Thesis: Instruction set extensions for Dynamic Time Warping

http://dl.acm.org/citation.cfm?id=2555692.2555710

Pertinent Knowledge: Apprentice Teaching, Algorithms and Data Structures, Advanced Computer Architecture, Advanced Computer Networks, Artificial Intelligence, Compiler Construction, Computer-Aided Electronic Circuit Simulation, Data Mining Techniques, Design and Architecture of Computer Systems, Design of Operating Systems, Digital Circuit Design, Discrete Structures, Electronic Circuits, Embedded and Real-Time Systems, Logic Design, Machine Learning, Machine Organization, Modeling and Simulation, NAND Memory, Network Routing, Phase Change Memory, Software and Hardware Engineering of Embedded Systems, Software Engineering, Solid State Electronics, Synthesis of Digital Systems, Reconfigurable Computing, Testing & Verification Techniques

B.S. Computer Engineering, UC Riverside

Adviser: Dr. Philip Brisk, Professor of Computer Science and Engineering

Focus: Computer Architecture and Embedded Systems

Project: Open RISC Processor Emulation Platform (FPGA)

Pertinent Knowledge: Assembly Programming, Algorithms, American Politics, Automata and Formal Languages, Biochemical Analysis, C++ Programming, Business Ethics, Formal Organizations, Concurrent Programming, Compiler Construction, Computer Architecture, Data Structures, Design of Integrated Circuits, Electrical Circuit Analysis, Embedded Systems, Logic Design, Machine Organization, Operating Systems, Modeling and Simulation of Dynamic Systems, Organic Chemistry, Real-Time Systems, Religious Myths and Rituals, Signals/Systems Analysis, Software and Hardware System Engineering, Solid State Electronics, Technical Communications, Technology in Pre-Modern civilizations, World History (Twentieth Century)

A.S. Double Major in Mathematics and Physics, Crafton Hills College

Adviser: Dr. Matthew Adams, Professor of Physics and Astronomy

Pertinent Knowledge: Applied Sciences Pertinent Knowledge: Mechanics (Classical, Quantum Relativistic, Statistical), Electromagnetism, Thermodynamics, and Quantum Theory Calculus (Differential, Integral, Series, Vector, Multivariable, Specialized) Linear Algebra, Probability, Statistics Chemistry, English Composition and Critical Analysis, Hardware and Information Systems, A-plus (A+), Philosophy of Ethics and Moral Virtues, Sociology

TECHNICAL EXPERTISE

Programming Languages C, C++, Perl, Python, and VHDL

Design Software Altera, Cadence, Green Hills Software, JetBrains, PSPICE, Synopsys, Synplify, and Xilinx

Operating Systems/Platforms UNIX, Linux, Ubuntu, DOS, Windows, and FreeRTOs.

PROFESSIONAL EXPERIENCE

Employment:

· Intel Corporation: Intel Boulder, CO. (2018-Present)

o Position: Machine Learning. Research Scientist in platform ecosystems using data mining, machine learning, artificial intelligence, and system architecture.

o Expertise: Arithmetic, Artificial Intelligence, Compilers, Computer Architecture, Data Mining, Similarity Search, Machine Learning, Numerical Analysis, Persistent Memory (Optane), and System Architecture.

o Focus:

§ Principal Investigator for Rapid Automation and Analysis for Developers (RAAD). A Machine Programming Product and Customer Acceleration Intelligent system. https://www.github.com/intel/raad

§ Co-Inventor of common telemetry architecture, reconfigurable architecture, and intelligence intervention systems.

§ LLVM Compiler Infrastructure (Optane) Persistent Memory extensions for C/C++ language.

§ Computation acceleration

o Technical Track Leadership:

§ Technical Lead for Persistent Memory domain in NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures (CAPA) NSF 16-606 https://www.nsf.gov/pubs/2016/nsf16606/nsf16606.htm

o Domain Expert Researcher for SiFive through Intel Capital:

§ Developed automated compilation flow and customs instruction application programming interface for data mining, artificial intelligence, machine learning, and similarity search. https://github.com/jtarango/freedom.git

o Company wide Mentor:

§ Focused mentoring for prodigy technical engineers.

o Division Recognition Award(s) and Recognition(s) (Sorted oldest to newest):

§ 2018, Inventor and co-developer of cross-language compiler to auto decode machine data structure source and destination targets using LLVM.

§ 2018, Architecture of common data management methodology across all data center products.

§ 2019, Co-development of a common architecture, rapidly prototyping, and delivering Telemetry in data center SSDs products.

§ 2019, Re-architecture and development of the content in the rapid analysis handbook.

§ 2020, Co-development of novel automation and tools.

§ 2020, Distinguished Inventor Patent Award for Deep Neural Network (DNN) technologies.

· University of Colorado, Boulder (CU) (2019)

o Position: Adjunct Professor and Industry Adviser

o Advanced computer architecture, artificial intelligence, machine learning instructor, and academic advisor for graduate level masters and Doctoral Candidates.

o Teaching: Computer Architecture

§ ECEN 5593 Advanced Computer Architecture

§ https://sites.google.com/view/ecen5593-2019-fall/home

· Intel Corporation: Intel Non-Volatile Memory Systems Group (NSG) in Longmont, CO. (2013-2018)

o Positions (Sorted oldest to newest):

§ Technical Product Lead of core/system algorithms; University Program Project Director for Outreach, Recruiting, and Research

§ System Technical Product Lead for Path-finding, Fault Analysis, Research, and Development Engineer

§ Artificial Intelligence and Machine Learning Pathfinding and System Technical Product Lead for PCIe/NVMe Enterprise based products in Non-Volatile Memory Systems Group (NSG).

o Focus: Proactive/reactive algorithms, optimization, technical risk analysis, customer request analysis, architecture pathfinding for productization, team organization, milestone technical planning for development-validation, and system integration (simulation, emulation, and ASIC platforms).

o Expertise: Standardized transport interfaces, Cache Management, Context State, Garbage Collection, Journaling, Media Policy, Mentoring, Modeling, Performance, Power Loss Imminent, Power Loss Recovery, Read Disturb, Shutdown, Time-To-Ready, Write Steam Management, Wear Leveling.

o NSG Award(s) and Recognition(s) (Sorted oldest to newest):

§ 2013, Driving quality and reliability in Intel's first data center NVMe DC P3700 SSD.

§ 2013, Power management integrated circuit (PMIC) firmware for data center SSDs.

§ 2014, Robustness in garbage collection and wear-leveling in data center SSDs.

§ 2014, Robustness in power loss and recovery algorithms in data center SSDs.

§ 2015, Driving the delivery of the first 3D NAND NVMe DC P3520 SSD.

§ 2015, Delivering a novel contribution in characterization and optimizations of the performance of data center SSDs.

§ 2015, Co-delivering soft and hardware accelerated erase dwell time control systems.

§ 2016, Strategy Acceleration Division Recognition Award For establishing 3D Component and Solid State Drive (SSD) Models utilized by cross-platform teams within NSG and across Intel.

§ 2016, Delivering state of the art architecture for safe shutdown in data center SSDs.

§ 2016, Delivering device time to ready auto tuning in data center SSDs.

§ 2017, Performance characterization of Field Programmable Gate Array (FPGA) emulated SSD System-on-Chip (SoC).

§ 2017, Development of the fastest and most comprehensive simulation, emulation, and power-on of a data center SSD System-on-Chip (SoC).

§ 2018, Co-development of a common architecture, rapidly prototyping, and delivering Telemetry in data center SSDs products.

· Intel Corporation: Intel Non-Volatile Memory Systems Group (NSG) in Longmont, CO. (2013)

o Position: Proactive Team Intern

§ Non-Volatile Memory Solutions Group (NSG) for Solid State Drive (SSD) development in client and enterprise in relation to SATA, SAS, and NVMe interfaces.

o Roles and Responsibilities

§ Analytical analysis of architecture and algorithms.

§ Performance aware memory structures for fast path algorithms.

§ Automated testing methodologies enhancements, extensions, and profiling.

§ Algorithm hardening for enterprise applications for minimizing downtime.

§ Alpha, Beta, Gamma particle hardening co-design of System-on-Chip (SoC), firmware, and host using automated parity fault recovery of critical data structures in enterprise applications.

o Awards:

§ Intel Ph.D. Patronage (Unique and distinct NSG scholarship of Ph.D.)

· University of California, Riverside (2008-2018)

· Positions: Graduate Researcher, Teaching Assistant, Undergraduate Researcher

· Roles and Responsibilities:

o Customizable Extensions for Dynamic Time Warping

o Dynamic precision and range arithmetic library for scientific computing (Fixed-Point, Floating Point, and Logarithmic Arithmetic)

o Embedded Dynamic Time Warping in Logarithmic Arithmetic

o Embedded Dynamic Time Warping in Pipelined Floating-Point Arithmetic

o Shared Virtual Memory for Higher Performance Computing in CPU, GPU, and FPGA systems

o Virtualized Distributed Block RAM for FPGAs

o Hybrid-Reconfigurable Processor with tightly coupled RISC processor with custom instruction based reconfigurable accelerators. Collaboration with the National University of Singapore supported by the National Science Foundation. In conjunction with University of Bern and École polytechnique fédérale de Lausanne (EPFL).

o N-Way maximum parallel computing

o Generalized VHDL interfaces and optimizations for FPGAs with Riverside Optimizing Configurable Computing Compiler (ROCCC)

· Jacquard Computing: (2008 – 2010)

o Position: Researcher

o Role: High performance computing and FPGA interfaces for automated LLVM C language to VHDL synthesis/compilation applications using Convey, Pico, Intel, Altera, and Xilinx devices. Department of Defense (DoD) funded startup.

Leadership:

· Member and Advisor: Floating Point Benchmark Standards (FPBench)

· Advisor for National Science Foundation (NSF): Advisor for technical content and recommendations.

· Director: Systematized teams for Association of Computing Machinery programming competitions. Instructed teams on optimal communication techniques and how to efficiently code algorithms in C++.

· Technical Industry Panel for Colorado University: Industry panel to diverge a path for technical pipelines into industry.

· University Program Project Director for Outreach, Recruiting, and Research. Creation of technical content, projects, and enablement of novel courses to create a technical pipeline.

Patents Pending: https://uspto.report/patent/search/tarango,%20joseph

1. 20210191726. Methods And Apparatus For Continuous Monitoring Of Telemetry In The Field

2. 20210157512. Flexible Configuration Of Storage Device With Translation Language Set

3. 20210073632. Methods, Systems, Articles Of Manufacture, And Apparatus To Generate Code Semantics

4. 20200379687. Storage Device With Client Reconfigurable Protocol

5. 20200226080. Solid State Drive With External Software Execution To Effect Internal Solid-state Drive Operations

6. 20200225857. Techniques To Predict Or Determine Time-to-ready For A Storage Device

7. 20200218649. Performance Configurable Nonvolatile Memory Set

8. 20190043604. Multi-level Memory Repurposing

9. 11069425. Multi-level memory repurposing technology to process a request to modify a configuration of a persistent storage media

10. 20190042139. Moving Average Valid Content On SSD

11. 10795593, 20190042129. Technologies For Adjusting The Performance Of Data Storage Devices Based On Telemetry Data

12. 20190042128. Technologies Dynamically Adjusting The Performance Of A Data Storage Device

13. More pending…

Publications:

[CODES+ISSS] Instruction Set Extensions for Dynamic Time Warping

J. Tarango, E. Keogh, and P. Brisk International Conference on Hardware/Software Codesign and System Synthesis Montreal, Canada, September 29 -October 4, 2013.

[ICCAD] A Just-in-Time Customizable Processor

L. Chen, J. Tarango, T. Mitra, and P. Brisk International Conference on Computer-Aided Design San Jose, CA, USA, November 18-21, 2013

[ASILOMAR-SSC] Accelerating the Dynamic Time Warping Distance Measure using Logarithmic Arithmetic

J. Tarango, E. Keogh, and P. Brisk

Pacific Grove, CA, November 2-5, 2014

Teaching:

University of California, Riverside

· Teaching Assistant: CS5 Introduction to Computer Programming, Winter 2011

· Teaching Assistant: CS61 Machine Organization and Assembly Language Programming, Spring 2011

· Teaching Assistant: CS120B Introduction to Embedded Systems, Summer 2011

· Teaching Assistant: CS122A Intermediate Embedded and Real-Time Systems, Fall 2011

· Teaching Assistant: CS120B Introduction to Embedded Systems, Winter 2012

· Teaching Assistant: CS8 Introduction to Computing, Spring 2012

· Teaching Assistant: CS161 Design and Architecture of Computer Systems, Spring 2012

· Teaching Assistant: CS161L Design and Architecture of Computer Systems, Spring 2012

University of Colorado, Boulder

· Adjunct Mentor: ECEN 5013-003: ASIP and IP Core Processor Design, Winter 2018

· Adjunct Professor: ECEN 5593 Advanced Computer Architecture, Fall 2019

Research:

· Research Assistant for Dr. Walid Najjar (Professor) on Riverside Optimizing Compiler for Configurable Computing (ROCCC). ROCCC is a C to VHDL compiler, which enables C programs to be translated to high-speed FPGA platforms. Systems including: Intel-Altera, Convey, Pico, Xilinx FPGAs to generate system arithmetic data paths.

· Jacquard Computing Inc. structure standard interfaces for FPGA platforms.

· Research Assistant at Bern University of Applied Sciences (Switzerland) under the guidance of Dr. Theo Kluter (Professor) for RISC processor cache optimization techniques.

· Research Assistant developing the Clarity (EPFL, Switzerland) Compiler for customized processors. The platform profiled code, provided analyzed, instrumented summary of feasible optimizations, and generated custom IP blocks for embedded processors.

· Principal investigator on hybrid reconfigurable processor sponsored by National Science Foundation (NSF) in conjunction with National University of Singapore under Dr. Tulika Mitra (Professor)

· Arithmetic optimization through compiler and hardware accelerators; the projects included prototyping algorithms to run on tightly coupled ASIC/FPGA and computing systems for similarity search algorithms under Dr. Philip Brisk (Professor)

· Principal Investigator “Hybrid-Reconfigurable Processor (HR-P): An Efficient and Accelerated Embedded Architecture for Mobile Computing” NSF East Asia and Pacific Summer Institute for FY 2012 in Singapore https://www.nsf.gov/awardsearch/showAward?AWD_ID=1210182

· Technical Lead for Persistent Memory domain in NSF/Intel Partnership on Computer Assisted Programming for Heterogeneous Architectures (CAPA) NSF 16-606 https://www.nsf.gov/pubs/2016/nsf16606/nsf16606.htm

· Domain Expert Researcher for SiFive through Intel Capital - Developed automated compilation flow and customs instruction application programming interface for data mining, artificial intelligence, machine learning, and similarity search. https://github.com/jtarango/freedom.git

Internships:

· University of Bern: Under the guidance of Dr. Theo Kluter; worked on the VHDL implementation of (RISC) soft processor and compilation tool chain. (2011)

· National University of Singapore: Under the guidance of Dr. Tulika Mitra; Developed reconfigurable customized processor data paths based on detailed hot sequences within encryption, media, SPEC benchmarks. Reconfigurable custom data paths were developed to interface with ARM Cortex-A9 processors and SimpleScalar. (2012)

· Intel Corporation: Intel Technology and Manufacturing group in Longmont, CO. Worked with Intel Engineers to enhance Solid State Drive (SSD) performance. (2013)

Projects:

· Design Project: Designed a multi-stage audio amplifier from MOSFETs/BJTs to augment a small signal input to a high-power audio system. The stages included a: differential input, voltage amplification, and push-pull output.

· Implementation: Updated program interface for a reduced instruction set computer (Open RISC) soft-processor on a Custom Field Programmable Gate Array (FPGA) for Dr. Phillip Brisk (UC Riverside Professor).

INVOLVEMENT

Memberships and Associations

Member, Association of Computing Machinery (ACM)
Member, Institute of Electronics and Electrical Engineers (IEEE)
Member, Society of Hispanic Professional Engineers (SHEP)
Member, Alpha Gamma Sigma Honor Society (AGS)

Fellowships

Alliance for Graduate Education and the Professoriate Fellow
CCRAA Fellow
Dean’s Distinguished Fellow
NSF EASPI Fellow
Intel Full Ride Scholarship

Significant Awards

Diversity Award
EOPS/CARE/CalWorks Scholar Award
Hispanic Scholar Award

Volunteer Experience

Crafton Hills Aid for Unfortunate Families
Community Food Share in Boulder, Colorado
Joslyn Senior Center in Redlands, California
Math Tutor at Fontana High School and Crafton Hills College
MESA Day
Redlands High School Wrestling Team
Special Olympics of Southern California
UCR Bourns College of Engineering Family Night

Special Events

Graduate Research Day (Sacramento, CA 2013)

Special Presentations

A Just-in-Time Customizable Processor (UCR AGEP 2013) Accelerating Time-series Subsequences Using Instruction Set Extensions for Embedded Systems (UCR AGEP 2013)

References

Available upon request

Last updated: May 30, 2023